1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to an ESD protection circuit having a plurality of low-voltage gate trigger Silicon Controlled Rectifiers (SCRs) to eliminate electrostatic stress in semiconductor chip pads and avoid destruction of internal circuits.
2. Description of the Prior Art
The effect of electrostatic discharge (herein called ESD), which exists within an integrated circuit during the period of manufacture and use, is a severely destructive factor for an integrated circuit. The stress produced by ESD, passing through the pads of a chip to the internal circuits, may result in damage of the integrated circuit. Currently four models are used to explain the sources of ESD:
(1) the human body model, defined by the MIL-STD-883, Method 3015.6, which refers to the ESD stress produced by the human body carrying electrostatic touching the pins of a integrated circuit; PA1 (2) the machine model, followed by the test of the present industrial standard EIAJ-IC-121, Method 20, which refers to a machine carrying an electrostatic charge touching the pins of a integrated circuit; PA1 (3) the charged device model, which refers to an originally charged integrated circuit, which in subsequent steps contacts a conductive material to ground, resulting in an ESD impulse passing through the integrated circuit; and PA1 (4) the field-induced model, which refers to an electrostatic field inducing a potential between an integrated circuit and ground, then discharging to ground during the process of measuring and packaging. PA1 (a) PS (positive source) mode, wherein the ESD stress has positive polarity potential with respect to the reference low potential VSS, with the terminal of the reference high potential VDD floating; PA1 (b) NS (negative source) mode, wherein the ESD stress has negative polarity potential with respect to the reference low potential VSS, with the terminal of the reference high potential VDD floating; PA1 (c) PD (positive drain) mode, wherein the ESD stress has positive polarity potential with respect to the reference high potential VDD, with the terminal of the reference low potential VSS floating; PA1 (d) ND (negative drain) mode, wherein the ESD stress has negative polarity potential with respect to the reference high potential VDD, with the terminal of the reference low potential VSS floating.
Sometimes, an ESD protection circuit is coupled to the wire between the pads and the internal circuits to reduce the failure rate of integrated circuits caused by ESD stress and to ensure the reliability of the integrated circuits. In CMOS circuits, a protection circuit is usually implemented by a lateral silicon controlled rectifier (LSCR). Compatibility with the manufacturing process of a CMOS integrated circuit is the main advantage of this technology. But, for a 0.6-0.8 .mu./n submicron CMOS, the thickness of a gate oxide layer is about 150-200 .mu.m. If the field strength of breakdown, for example, is about 10 MV/cm2 in a dielectric SiO2, the gate oxide layer will be damaged under 15-20 V. Therefore, LSCR devices, whose trigger voltage is about 30-50 V, must be protected with additional protection devices to prevent the breakdown of the gate oxide layer.
LSCR devices can constitute the ESD protection circuit. However, especially in a submicron process, the trigger voltage of a parasitic LSCR device is much larger than the breakdown voltage of the gate oxide layer due to shrinkage of the device size, so it can not provide adequate ESD protection. A parasitic LSCR having a low trigger voltage is necessary to prevent the above phenomenon. A methodology described in the article entitled "A low-voltage triggering SCR for on-chip ESD protection at output and input pads", in proc. 1990 Symposium on VLSI Tech., pp. 75-56, by A. Chatterjee and T. Polgreen, adopts a novel low-voltage trigger SCR (LVTSCR) to improve upon the drawbacks of a conventional LSCR device. The LVTSCR device having the lower trigger voltage includes a traditional LSCR device and an NMOS short channel transistor. The phenomena of snapback breakdown, which is distinctive of the LVTSCR device, is applied to reduce the trigger voltage of the LVTSCR device to the breakdown voltage (BVdss) of the short channel NMOS transistor.
While an ESD protection circuit consisting of a conventional LVTSCR device provides an apparent improvement of the trigger voltage, nonetheless, there are still limitations in its application as the ESD protection circuit in a integrated circuit.
To help understand the limitations, the various forms of ESD stress need to be briefly discussed. For a reference high potential VDD and a reference low potential VSS (or ground), the ESD stress can be classified as positive polarity or negative polarity. Accordingly, on every pad in a general integrated circuit, four different modes of ESD stress can be identified as:
MOS transistors in a input stage or an output driver of an integrated circuit may be damaged by means of any of the above-mentioned four modes of the ESD stress. The ESD protection circuit in the conventional technology is located between the pad and the reference low potential VSS and there is no direct discharge path between the pad and the reference high potential VDD. In the case of the PD mode and ND mode of ESD stress, for example, there is a potential of positive or negative polarity for the ESD stress between the pad and the reference high potential VDD when the reference low potential VSS is floating. This potential of the ESD stress will be discharged through the following path: the pad, the LVTSCR device in the ESD protection circuit, the reference low potential VSS, another protection circuit between the reference low voltage and the reference high voltage, and the reference high potential VDD. However, there are many parasitic resistors and capacitors within the power line. Therefore an indirect discharge due to the parasitic effect may be harmful to the internal circuitry of the integrated circuit.
Although the trigger voltage is reduced to the breakdown voltage of the short channel NMOS transistor, LVGTSCR devices provide insufficient protection since we cannot make sure whether the ESDstress has been bypassed through the ESD protection circuit and is harmless to the input stage and output driving stage.
Further, since integration and shrinkage is the main future trend in integrated circuit, a conventional ESD protection circuit using LVGTSCR devices is inappropriate for the submicron process and low-voltage ICs because of the difficulty in adjusting the trigger voltage.
Finally, the LVTSCR device chooses the snapback mode of a short channel NMOS transistor as the operation mode for bypassing ESD. However, this operation mode is not the best one for protecting from ESD for limited current capability.